Hynix HMT31GR7CFR4A-PBT8 Datasheet download pdf (Page 6)

Rev. 1.1 / May. 2013 6

Input/Output Functional Descriptions

Symbol Type Polarity Function

CK0 IN

Positive

Line

Positive line of the differential pair of system clock inputs that drives input to the on-

DIMM Clock Driver.

CK0

Negative

Line

Negative line of the differential pair of system clock inputs that drives the input to the

on-DIMM Clock Driver.

CK1 IN

Positive

Line

Terminated but not used on RDIMMs.

CK1

Negative

Line

Terminated but not used on RDIMMs.

CKE[1:0] IN

Active

High

CKE HIGH activates, and CKE LOW deactivates internal clock signals, and device input

buffers and output drivers of the SDRAMs. Taking CKE LOW provides PRECHARGE

POWER-DOWN and SELF REFRESH operation (all banks idle), or ACTIVE POWER DOWN

(row ACTIVE in any bank)

[3:0] IN

Active

Low

Enables the command decoders for the associated rank of SDRAM when low and dis-

ables decoders when high. When decoders are disabled, new commands are ignored

and previous operations continue. Other combinations of these input signals perform

unique functions, including disabling all outputs (except CKE and ODT) of the register(s)

on the DIMM or accessing internal control words in the register device(s). For modules

with two registers, S[3:2]

operate similarly to S[1:0] for the second set of register out-

puts or register control words.

ODT[1:0] IN

Active

High

On-Die Termination control signals

AS, CAS, WE IN

Active

Low

When sampled at the positive rising edge of the clock, CAS

, RAS, and WE define the

operation to be executed by the SDRAM.

REFDQ

Supply Reference voltage for DQ0-DQ63 and CB0-CB7.

REFCA

Supply

Reference voltage for A0-A15, BA0-BA2, RAS

, CAS, WE, S0, S1, CKE0, CKE1, Par_In,

ODT0 and ODT1.

BA[2:0] IN —

Selects which SDRAM bank of eight is activated.

BA0 - BA2 define to which bank an Active, Read, Write or Precharge command is being

applied. Bank address also determines mode register is to be accessed during an MRS

cycle.

A[15:13,

12/BC

,11,

10/AP,[9:0]

IN —

Provided the row address for Active commands and the column address

and Auto Precharge bit for Read/Write commands to select one location out of the mem-

ory array in the respective bank. A10 is sampled during a Precharge command to deter-

mine whether the Precharge applies to one bank (A10 LOW) or all banks (A10 HIGH). If

only one bank is to be precharged, the bank is selected by BA. A12 is also utilized for BL

4/8 identification for ‘’BL on the fly’’ during CAS

command. The address inputs also pro-

vide the op-code during Mode Register Set commands.

DQ[63:0],

CB[7:0]

I/O — Data and Check Bit Input/Output pins

DM[8:0] IN

Active

High

Masks write data when high, issued concurrently with input data.

, V

Supply Power and ground for the DDR SDRAM input buffers and core logic.

Supply Termination Voltage for Address/Command/Control/Clock nets.

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Hynix HMT31GR7CFR4A-PBT8 Datasheet Page 6

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