Hynix HMT31GR7CFR4A-PBT8 Datasheet Page 27
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Rev. 1.1 / May. 2013 27
16GB, 2Gx72 Module(4Rank of x4) - page5
CK1
CK1
120
Ω
±5%
S2
S3
BA[N:0]
A[N:0]
RAS
CAS
WE
CKE0
CK0
CK0
PAR_IN
BRS2A
→
CS1: SDRAMs D45,D47,D49,D51,D53
BRS2B
→
CS1: SDRAMs D37,D39,D41,D43,
BRS3A
→
CS0: SDRAMs D44.D46,D48,D50,D52,
BRRASB
→
RAS: SDRAMs D[43:36],D[61:54]
BRS3B
→
CS0: SDRAMs D36,D38,D40,D42,
BRBA[N:0]B
→
BA[N:0]: SDRAMs D[43:36],D[61:54]
BRBA[N:0]A
→
BA[N:0]: SDRAMs D[53:44],D[71:62]
BRRASA
→
RAS: SDRAMs D[53:44],D[71:62]
BRCASB
→
CAS: SDRAMs D[43:36],D[61:54]
BRCASA
→
CAS: SDRAMs D[53:44],D[71:62]
BRWEB
→
WE: SDRAMs D[43:36],D[61:54]
BRWEA
→
WE: SDRAMs D[53:44],D[71:62]
BRCKE0B
→
CKE1: SDRAMs D37,D39,D41,D43,
BRCKE0A
→
CKE1: SDRAMs D45,D47,D49,D51,D53,
BRODT1B
→
ODT0: SDRAMs D37,D39,D41,D43
BRODT1A
→
ODT1: SDRAMs D45,D47,D49,D51,D53
BPCK0B
→
CK: SDRAMs D[43:36]
BPCK0A
→
CK: SDRAMs D[53:44]
BPCK0B
→
CK: SDRAMs D[43:36]
BPCK0A
→
CK: SDRAMs D[53:44]
Err_Out
RESET RST
1:2
R
E
G
I
S
T
E
R
/
P
BRCKE1B
→
CKE0: SDRAMs D36,D38,D40,D42,
BRCKE1A
→
CKE0: SDRAMs D44.D46,D48,D50,D52,
ODT1
CKE1
BRA[N:0]B
→
A[N:0]: SDRAMs D[43:36],D[61:54]
BRA[N:0]A
→
A[N:0]: SDRAMs D[55:44],D[71:62]
BPCK1B
→
CK: SDRAMs D[61:54]
BPCK1A
→
CK: SDRAMs D[71:62]
BPCK1B
→
CK: SDRAMs D[61:54]
BPCK1A
→
CK: SDRAMs D[71:62]
L
L
B
D63,D65,D67,D69,D71
D55,D57,D59,D61
D62,D64,D66,D68,D70
D54,D56,D58,D60
D63,D65,D67,D69,D71
D55,D57,D59,D61
D62,D64,D66,D68,D70
D54,D56,D58,D60
D63,D65,D67,D69,D71
D55,D57,D59,D61
120
Ω
±5%
S0
S1
BA[N:0]
A[N:0]
RAS
CAS
WE
CKE0
CK0
CK0
PAR_IN
ARS0A
→
CS1: SDRAMs D1,D3,D5,D7 D9,
ARS0B
→
CS1: SDRAMs D11, D13, D15, D17,
ARS1A
→
CS0: SDRAMs D0, D2, D4, D6, D8,
ARRASB
→
RAS: SDRAMs D[17:10],D[35:28]
ARS1B
→
CS0: SDRAMs D10, D12, D14, D16,
ARBA[N:0]B
→
BA[N:0]: SDRAMs D[17:10],D[35:28]
ARBA[N:0]A
→
BA[N:0]: SDRAMs D[9:0],D[27:18]
ARRASA
→
RAS: SDRAMs D[9:0],D[27:18]
ARCASB
→
CAS: SDRAMs D[17:10],D[35:28]
ARCASA
→
CAS: SDRAMs D[9:0],D[27:18]
ARWEB
→
WE: SDRAMs D[17:10],D[35:28]
ARWEA
→
WE: SDRAMs D[9:0],D[27:18]
ARCKE0B
→
CKE1: SDRAMs D11,D13,D15,D17,
ARCKE0A
→
CKE1: SDRAMs D1,D3,D5,D7,D9,
ARODT0B
→
ODT0: SDRAMs D11,D13,D15,D17,
ARODT0A
→
ODT1: SDRAMs D1,D3,D5,D7,D9,
APCK0B
→
CK: SDRAMs D[17:10]
APCK0A
→
CK: SDRAMs D[9:0]
APCK0B
→
CK: SDRAMs D[17:10]
APCK0A
→
CK: SDRAMs D[9:0]
Err_Out
RESET RST
RST: SDRAMs D[35:0]
1:2
R
E
G
I
S
T
E
R
/
P
ARCKE1B
→
CKE0: SDRAMs D10,D12,D14,D16,
ARCKE1A
→
CKE0: SDRAMs D0,D2,D4,D6,D8,
ODT0
CKE1
ARA[N:0]B
→
A[N:0]: SDRAMs D[17:10],D[35:28]
ARA[N:0]A
→
A[N:0]: SDRAMs D[9:0],D[27:18]
APCK1B
→
CK: SDRAMs D[35:28]
APCK1A
→
CK: SDRAMs D[27:18]
APCK1B
→
CK: SDRAMs D[35:28]
APCK1A
→
CK: SDRAMs D[27:18]
L
L
A
D19, D21, D23, D25, D27
D29, D31, D33, D35
D18, D20, D22, D24, D26
D28, D30, D32, D34
D19, D21, D23, D25, D27
D29, D31, D33, D35
D18, D20, D22, D24, D26
D28, D30, D32, D34
D19, D21, D23, D25, D27
D29, D31, D33, D35
120
Ω
±5%
1. CK0 and CK0 are differentially terminated with a single
120 Ohms ±5% resistor.
2.
CK1 and CK1 are differentially terminated with a single
120 Ohms ±5% resistor, but is not used.
3. Unused register inputs ODT1 for Register A and ODT0 for Register B are tied to ground.
4. The module drawing on this page is not drawn to scale.
- DDR3L SDRAM Registered DIMM 1
- Based on 2Gb C-die 1
- Revision History 2
- Description 3
- Features 3
- Ordering Information 3
- Key Parameters 4
- Speed Grade 4
- Address Table 4
- Pin Descriptions 5
- Symbol Type Polarity Function 6
- Pin Assignments 8
- Capacitance Values 10
- On DIMM Thermal Sensor 11
- Functional Block Diagram 12
- Rev. 1.1 / May. 2013 14 14
- Rev. 1.1 / May. 2013 15 15
- Rev. 1.1 / May. 2013 16 16
- Rev. 1.1 / May. 2013 17 17
- Rev. 1.1 / May. 2013 18 18
- Rev. 1.1 / May. 2013 19 19
- Rev. 1.1 / May. 2013 20 20
- Rev. 1.1 / May. 2013 22 22
- Rev. 1.1 / May. 2013 23 23
- Rev. 1.1 / May. 2013 24 24
- Rev. 1.1 / May. 2013 25 25
- Rev. 1.1 / May. 2013 27 27
- Absolute Maximum Ratings 28
- Rev. 1.1 / May. 2013 29 29
- Rev. 1.1 / May. 2013 30 30
- Rev. 1.1 / May. 2013 31 31
- Rev. 1.1 / May. 2013 32 32
- Vref Tolerances 33
- Rev. 1.1 / May. 2013 35 35
- Rev. 1.1 / May. 2013 36 36
- Rev. 1.1 / May. 2013 37 37
- Rev. 1.1 / May. 2013 38 38
- Measured 39
- Rev. 1.1 / May. 2013 40 40
- Single Ended Output Slew Rate 41
- Differential Output Slew Rate 42
- Rev. 1.1 / May. 2013 43 43
- Rev. 1.1 / May. 2013 44 44
- (CK, CK, DQ, DQS, DQS, DM) 45
- Rev. 1.1 / May. 2013 46 46
- Standard Speed Bins 47
- DDR3L-1066 Speed Bins 48
- DDR3L-1333 Speed Bins 49
- DDR3L-1600 Speed Bins 50
- Speed Bin Table Notes 51
- Environmental Parameters 52
- Rev. 1.1 / May. 2013 53 53
- ILAC(max) 53
- IHAC(max) 53
- Rev. 1.1 / May. 2013 54 54
- Rev. 1.1 / May. 2013 55 55
- Symbol Description 56
- Rev. 1.1 / May. 2013 59 59
- Rev. 1.1 / May. 2013 60 60
- Rev. 1.1 / May. 2013 61 61
- Rev. 1.1 / May. 2013 62 62
- Rev. 1.1 / May. 2013 63 63
- Rev. 1.1 / May. 2013 65 65
- Rev. 1.1 / May. 2013 66 66
- Rev. 1.1 / May. 2013 67 67
- Module Dimensions 68
- Units: millimeters 69
- 33.4 33.4 72
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