Hynix HMT31GR7CFR4A-PBT8 Datasheet Page 12
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Rated. / 5. Based on customer reviews
Rev. 1.1 / May. 2013 12
Functional Block Diagram
2GB, 256Mx72 Module(1Rank of x8)
CB[7:0]
DQS8
DQS8
DM8/DQS17
DQS17
RRASA
RCASA
RS0A
RWEA
PCK0A
PCK0A
RCKE0A
RODT0A
A[N:O]A
Vtt
DQ[31:24]
DQS3
DQS3
DM3/DQS12
DQS12
DQ[23:16]
DQS2
DQS2
DM2/DQS11
DQS11
DQ[15:8]
DQS1
DQS1
DM1/DQS10
DQS10
DQ[7:0]
DQS0
DQS0
DM0/DQS9
DQS9
DQS
DQS
TDQS
TDQS
D8
DQ [7:0]
ZQ
RAS
CAS
CS
WE
CK
CK
CKE
ODT
A[N:O]/BA[N:O]
DQS
DQS
TDQS
TDQS
D3
DQ [7:0]
ZQ
RAS
CAS
CS
WE
CK
CK
CKE
ODT
A[O:N]/BA[N:O]
DQS
DQS
TDQS
TDQS
D2
DQ [7:0]
ZQ
RAS
CAS
CS
WE
CK
CK
CKE
ODT
A[O:N]/BA[N:O]
DQS
DQS
TDQS
TDQS
D1
DQ [7:0]
ZQ
RAS
CAS
CS
WE
CK
CK
CKE
ODT
A[N:O]/BA[N:O]
DQS
DQS
TDQS
TDQS
D0
DQ [7:0]
ZQ
RAS
CAS
CS
WE
CK
CK
CKE
ODT
A
[N
:O]/BA[N:O]
DQ[39:32]
DQS4
DQS4
DM4/DQS13
DQS13
RRASB
RCASB
RS0B
RWEB
PCK0B
PCK0B
RCKE0B
RODT0B
A[N:O]B
Vtt
DQ[47:40]
DQS5
DQS5
DM5/DQS14
DQS14
DQ[55:48]
DQS6
DQS6
DM6/DQS15
DQS15
DQ[63:56]
DQS7
DQS7
DM7/DQS16
DQS16
DQS
DQS
TDQS
TDQS
D4
DQ [7:0]
ZQ
RAS
CAS
CS
WE
CK
CK
CKE
ODT
A[O:N]/BA[O:N]
DQS
DQS
TDQS
TDQS
D5
DQ [7:0]
ZQ
RAS
CAS
CS
WE
CK
CK
CKE
ODT
A[O:N]/BA[N:O]
DQS
DQS
TDQS
TDQS
D6
DQ [7:0]
ZQ
RAS
CAS
CS
WE
CK
CK
CKE
ODT
A[O:N]/BA[N:O]
DQS
DQS
TDQS
TDQS
D7
DQ [7:0]
ZQ
RAS
CAS
CS
WE
CK
CK
CKE
ODT
A[N:O]/BA[N:O]
/BA[N:O]A
/BA[N:O]B
S0
S1
BA[N:0]
A[N:0]
RAS
CAS
WE
CKE0
ODT0
CK0
CK0
PAR_IN
RS0A
→
CS0: SDRAMs D[3:0], D8
RS0B
→
CS0: SDRAMs D[7:4]
RBA[N:0]A
→
BA[N:0]: SDRAMs D[3:0], D8
RRASA
→
RAS: SDRAMs D[7:4]
RBA[N:0]A
→
BA[N:0]: SDRAMs D[7:4]
RA[N:0]A
→
A[N:0]: SDRAMs D[7:4]
RA[N:0]A
→
A[N:0]: SDRAMs D[3:0], D8
RRASA
→
RAS: SDRAMs D[3:0], D8
RCASA
→
CAS: SDRAMs D[7:4]
RCASA
→
CAS: SDRAMs D[3:0], D8
RWEA
→
WE: SDRAMs D[7:4]
RWEA
→
WE: SDRAMs D[3:0], D8
RCKE0B
→
CKE0: SDRAMs D[7:4]
RCKE0A
→
CKE0: SDRAMs D[3:0], D8
RODT0B
→
ODT0: SDRAMs D[7:4]
RODT0A
→
ODT0: SDRAMs D[3:0], D8
PCK0B
→
CK: SDRAMs D[7:4]
PCK0A
→
CK: SDRAMs D[3:0], D8
PCK0B
→
CK: SDRAMs D[7:4]
PCK0A
→
CK: SDRAMs D[3:0], D8
Err_Out
OERR
RESET
RST
RST: SDRAMs D[8:0]
S[3:2], CKE1, ODT1, are NC (Unused register inputs ODT1 and CKE1 have a 330
Ω
resistor to ground
1:
2
R
E
G
I
S
T
E
R
/
P
D0–D8
V
DD
V
TT
V
DDSPD
D0–D8
VREFDQ
SPD
VREFCA
V
SS
D0–D8
D0–D8
Note:
1.DQ-to-I/O wiring may be changed within byte.
2.ZQ resistors are 240
Ω±1%.For all other resistor values refer to the
appropriate wiring diagram.
VDDSPD
EVENT
SCL
SDA
SA0
SPD with
Integrated
TS
SA1
SA2
VSS
VDDSPD
EVENT
SCL
SDA
SA0
SA1
SA2
VSS
Plan to use SPD with Integrated TS of Class B and
might be changed on customer’s requests. For more
details of SPD and Thermal sensor, please contact
local SK hynix sales representative
120
Ω
±
1%
CK0
CK0
120
Ω
±
1%
L
L
- DDR3L SDRAM Registered DIMM 1
- Based on 2Gb C-die 1
- Revision History 2
- Description 3
- Features 3
- Ordering Information 3
- Key Parameters 4
- Speed Grade 4
- Address Table 4
- Pin Descriptions 5
- Symbol Type Polarity Function 6
- Pin Assignments 8
- Capacitance Values 10
- On DIMM Thermal Sensor 11
- Functional Block Diagram 12
- Rev. 1.1 / May. 2013 14 14
- Rev. 1.1 / May. 2013 15 15
- Rev. 1.1 / May. 2013 16 16
- Rev. 1.1 / May. 2013 17 17
- Rev. 1.1 / May. 2013 18 18
- Rev. 1.1 / May. 2013 19 19
- Rev. 1.1 / May. 2013 20 20
- Rev. 1.1 / May. 2013 22 22
- Rev. 1.1 / May. 2013 23 23
- Rev. 1.1 / May. 2013 24 24
- Rev. 1.1 / May. 2013 25 25
- Rev. 1.1 / May. 2013 27 27
- Absolute Maximum Ratings 28
- Rev. 1.1 / May. 2013 29 29
- Rev. 1.1 / May. 2013 30 30
- Rev. 1.1 / May. 2013 31 31
- Rev. 1.1 / May. 2013 32 32
- Vref Tolerances 33
- Rev. 1.1 / May. 2013 35 35
- Rev. 1.1 / May. 2013 36 36
- Rev. 1.1 / May. 2013 37 37
- Rev. 1.1 / May. 2013 38 38
- Measured 39
- Rev. 1.1 / May. 2013 40 40
- Single Ended Output Slew Rate 41
- Differential Output Slew Rate 42
- Rev. 1.1 / May. 2013 43 43
- Rev. 1.1 / May. 2013 44 44
- (CK, CK, DQ, DQS, DQS, DM) 45
- Rev. 1.1 / May. 2013 46 46
- Standard Speed Bins 47
- DDR3L-1066 Speed Bins 48
- DDR3L-1333 Speed Bins 49
- DDR3L-1600 Speed Bins 50
- Speed Bin Table Notes 51
- Environmental Parameters 52
- Rev. 1.1 / May. 2013 53 53
- ILAC(max) 53
- IHAC(max) 53
- Rev. 1.1 / May. 2013 54 54
- Rev. 1.1 / May. 2013 55 55
- Symbol Description 56
- Rev. 1.1 / May. 2013 59 59
- Rev. 1.1 / May. 2013 60 60
- Rev. 1.1 / May. 2013 61 61
- Rev. 1.1 / May. 2013 62 62
- Rev. 1.1 / May. 2013 63 63
- Rev. 1.1 / May. 2013 65 65
- Rev. 1.1 / May. 2013 66 66
- Rev. 1.1 / May. 2013 67 67
- Module Dimensions 68
- Units: millimeters 69
- 33.4 33.4 72
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