Hynix HMT31GR7CFR4A-PBT8 Datasheet Page 4

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Rev. 1.1 / May. 2013 4
Key Parameters
*SK hynix DRAM devices support optional downbinning to CL9 and CL7. SPD setting is programmed to match.
Speed Grade
Address Table
MT/s Grade
tCK
(ns)
CAS
Latency
(tCK)
tRCD
(ns)
tRP
(ns)
tRAS
(ns)
tRC
(ns)
CL-tRCD-tRP
DDR3L-1066 -G7 1.875 7 13.125 13.125 37.5 50.625 7-7-7
DDR3L-1333 -H9 1.5 9
13.5
(13.125)*
13.5
(13.125)*
36
49.5
(49.125)*
9-9-9
DDR3L-1600 -PB 1.25 11
13.75
(13.125)*
13.75
(13.125)*
35
48.75
(48.125)*
11-11-11
Grade
Frequency [MHz]
Remark
CL6 CL7 CL8 CL9 CL10 CL11
-G7 800 1066 1066
-H9 800 1066 1066 1333 1333
-PB 800 1066 1066 1333 1333 1600
2GB(1Rx8) 4GB(2Rx8) 4GB(1Rx4) 8GB(4Rx8) 8GB(2Rx4) 16GB(4Rx4)
Refresh
Method
8K/64ms 8K/64ms 8K/64ms 8K/64ms 8K/64ms 8K/64ms
Row Address A0-A14 A0-A14 A0-A14 A0-A14 A0-A14 A0-A14
Column
Address
A0-A9 A0-A9 A0-A9,A11 A0-A9 A0-A9,A11 A0-A9,A11
Bank Address BA0-BA2 BA0-BA2 BA0-BA2 BA0-BA2 BA0-BA2 BA0-BA2
Page Size 1KB1KB1KB1KB1KB1KB
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