Hynix HMT31GR7CFR4A-PBT8 Datasheet Page 56
- Page / 76
- Table of contents
- BOOKMARKS
Rated. / 5. Based on customer reviews
Rev. 1.1 / May. 2013 56
I
DD2N
Precharge Standby Current
CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8
a)
; AL: 0; CS: stable at 1; Command, Address, Bank
Address Inputs: partially toggling according to Table 5; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all
banks closed; Output Buffer and RTT: Enabled in Mode Registers
b)
; ODT Signal: stable at 0; Pattern Details:
see Table 5.
I
DD2NT
Precharge Standby ODT Current
CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8
a)
; AL: 0; CS: stable at 1; Command, Address, Bank
Address Inputs: partially toggling according to Table 6; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all
banks closed; Output Buffer and RTT: Enabled in Mode Registers
b)
; ODT Signal: toggling according to Table 6;
Pattern Details: see Table 6.
I
DD2P0
Precharge Power-Down Current Slow Exit
CKE: Low; External clock: On; tCK, CL: see Table 1; BL: 8
a)
; AL: 0; CS: stable at 1; Command, Address, Bank
Address Inputs: stable at 0; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all banks closed; Output Buf-
fer and RTT: Enabled in Mode Registers
b)
; ODT Signal: stable at 0; Precharge Power Down Mode: Slow Exit
c)
I
DD2P1
Precharge Power-Down Current Fast Exit
CKE: Low; External clock: On; tCK, CL: see Table 1; BL: 8
a)
; AL: 0; CS: stable at 1; Command, Address, Bank
Address Inputs: stable at 0; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all banks closed; Output Buf-
fer and RTT: Enabled in Mode Registers
b)
; ODT Signal: stable at 0; Precharge Power Down Mode: Fast Exit
c)
I
DD2Q
Precharge Quiet Standby Current
CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8
a)
; AL: 0; CS: stable at 1; Command, Address, Bank
Address Inputs: stable at 0; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all banks closed; Output Buf-
fer and RTT: Enabled in Mode Registers
b)
; ODT Signal: stable at 0
I
DD3N
Active Standby Current
CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8
a)
; AL: 0; CS: stable at 1; Command, Address, Bank
Address Inputs: partially toggling according to Table 5; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all
banks open; Output Buffer and RTT: Enabled in Mode Registers
b)
; ODT Signal: stable at 0; Pattern Details: see
Table 5.
I
DD3P
Active Power-Down Current
CKE: Low; External clock: On; tCK, CL: see Table 1; BL: 8
a)
; AL: 0; CS: stable at 1; Command, Address, Bank
Address Inputs: stable at 0; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all banks open; Output Buffer
and RTT: Enabled in Mode Registers
b)
; ODT Signal: stable at 0
Symbol Description
- DDR3L SDRAM Registered DIMM 1
- Based on 2Gb C-die 1
- Revision History 2
- Description 3
- Features 3
- Ordering Information 3
- Key Parameters 4
- Speed Grade 4
- Address Table 4
- Pin Descriptions 5
- Symbol Type Polarity Function 6
- Pin Assignments 8
- Capacitance Values 10
- On DIMM Thermal Sensor 11
- Functional Block Diagram 12
- Rev. 1.1 / May. 2013 14 14
- Rev. 1.1 / May. 2013 15 15
- Rev. 1.1 / May. 2013 16 16
- Rev. 1.1 / May. 2013 17 17
- Rev. 1.1 / May. 2013 18 18
- Rev. 1.1 / May. 2013 19 19
- Rev. 1.1 / May. 2013 20 20
- Rev. 1.1 / May. 2013 22 22
- Rev. 1.1 / May. 2013 23 23
- Rev. 1.1 / May. 2013 24 24
- Rev. 1.1 / May. 2013 25 25
- Rev. 1.1 / May. 2013 27 27
- Absolute Maximum Ratings 28
- Rev. 1.1 / May. 2013 29 29
- Rev. 1.1 / May. 2013 30 30
- Rev. 1.1 / May. 2013 31 31
- Rev. 1.1 / May. 2013 32 32
- Vref Tolerances 33
- Rev. 1.1 / May. 2013 35 35
- Rev. 1.1 / May. 2013 36 36
- Rev. 1.1 / May. 2013 37 37
- Rev. 1.1 / May. 2013 38 38
- Measured 39
- Rev. 1.1 / May. 2013 40 40
- Single Ended Output Slew Rate 41
- Differential Output Slew Rate 42
- Rev. 1.1 / May. 2013 43 43
- Rev. 1.1 / May. 2013 44 44
- (CK, CK, DQ, DQS, DQS, DM) 45
- Rev. 1.1 / May. 2013 46 46
- Standard Speed Bins 47
- DDR3L-1066 Speed Bins 48
- DDR3L-1333 Speed Bins 49
- DDR3L-1600 Speed Bins 50
- Speed Bin Table Notes 51
- Environmental Parameters 52
- Rev. 1.1 / May. 2013 53 53
- ILAC(max) 53
- IHAC(max) 53
- Rev. 1.1 / May. 2013 54 54
- Rev. 1.1 / May. 2013 55 55
- Symbol Description 56
- Rev. 1.1 / May. 2013 59 59
- Rev. 1.1 / May. 2013 60 60
- Rev. 1.1 / May. 2013 61 61
- Rev. 1.1 / May. 2013 62 62
- Rev. 1.1 / May. 2013 63 63
- Rev. 1.1 / May. 2013 65 65
- Rev. 1.1 / May. 2013 66 66
- Rev. 1.1 / May. 2013 67 67
- Module Dimensions 68
- Units: millimeters 69
- 33.4 33.4 72
Related products and manuals for Memory modules Hynix HMT31GR7CFR4A-PBT8
(23 pages)
Memory modules Hynix MM1263053 Datasheet
(27 pages)
© 2020, manymanuals.com. All rights reserved. | 0.596 s |
Manymanuals.com
Manymanuals.de
Manymanuals.fr
Manymanuals.it
Manymanuals.pl
Manymanuals.cz
Manymanuals.es
Manymanuals-pt.com
Comments to this Manuals