Hynix HMT351U7CFR8A-PBT0 Datasheet

Rev. 1.1 / Jul. 2013 1 240pin DDR3L SDRAM Unbuffered DIMM* SK hynix Semiconductor reserves the right to change products or specifications without not

Rev. 1.1 / Jul. 2013 10 On DIMM Thermal SensorThe DDR3L SDRAM DIMM temperature is monitored by integrated thermal sensor. The integrated thermal senso

Rev. 1.1 / Jul. 2013 11 Functional Block Diagram2GB, 256Mx72 Module(1Rank of x8)DQ4DQ5DQ6DQ7DQ0DQ1DQ2DQ3DMI/O 0I/O 1I/O 2I/O 3D0DM0I/O 4I/O 5I/O 6I/O

Rev. 1.1 / Jul. 2013 12 4GB, 512Mx72 Module(2Rank of x8) DQ4DQ5DQ6DQ7DQ0DQ1DQ2DQ3I/O 1I/O 2I/O 3D0D9I/O 4I/O 5I/O 6I/O 7I/O 0I/O 1I/O 2I/O 3I/O 4I/O 5

Rev. 1.1 / Jul. 2013 13 Absolute Maximum RatingsAbsolute Maximum DC RatingsNotes:1. Stresses greater than those listed under “Absolute Maximum Ratings

Symbol ParameterRatingUnits NotesMin. Typ. Max.Supply VoltageSupply Voltage for Output1. If minimum limit is exceeded, input levels shall be governed

Rev. 1.1 / Jul. 2013 15 Figure 0 - VDD/VDDQ Voltage Switch Between DDR3L and DDR3NOTE 1: From time point “Td” until “Tk” NOP or DES commands must be a

Rev. 1.1 / Jul. 2013 16 AC & DC Input Measurement LevelsAC and DC Logic Input Levels for Single-Ended SignalsAC and DC Input Levels for Single-End

Rev. 1.1 / Jul. 2013 17 AC and DC Input Levels for Single-Ended SignalsDDR3 SDRAM will support two Vih/Vil AC levels for DDR3-800 and DDR3-1066s speci

Rev. 1.1 / Jul. 2013 18 Vref TolerancesThe dc-tolerance limits and ac-noise limits for the reference voltages VRefCA and VRefDQ are illustrated in fig

Rev. 1.1 / Jul. 2013 19 AC and DC Logic Input Levels for Differential SignalsDifferential signal definitionDefinition of differential ac-swing and “ti

Rev. 1.1 / Jul. 2013 2 Revision HistoryRevision No. History Draft Date Remark0.1 Initial Release Aug. 20110.2 Added Speed Bin Table Notes Sep. 20110.3

Rev. 1.1 / Jul. 2013 20 Differential swing requirements for clock (CK - CK) and strobe (DQS-DQS)Notes:1. Used to define a differential signal slew-rat

Rev. 1.1 / Jul. 2013 21 Single-ended requirements for differential signalsEach individual component of a differential signal (CK, DQS, DQSL, DQSU, CK,

Symbol ParameterDDR3L-800, 1066, 1333, & 1600Unit NotesMin MaxVSEHSingle-ended high level for strobes (VDD / 2) + 0.175 Note 3 V 1,2Single-ended h

Rev. 1.1 / Jul. 2013 23 Differential Input Cross Point VoltageTo guarantee tight setup and hold times as well as output skew parameters with respect t

Rev. 1.1 / Jul. 2013 24 Slew Rate Definitions for Single-Ended Input SignalsSee 7.5 “Address / Command Setup, Hold and Derating” in “DDR3L Device Oper

Rev. 1.1 / Jul. 2013 25 AC & DC Output Measurement LevelsSingle Ended AC and DC Output LevelsTable below shows the output levels used for measurem

Rev. 1.1 / Jul. 2013 26 Single Ended Output Slew RateWhen the Reference load for timing measurements, output slew rate for falling and rising edges is

Rev. 1.1 / Jul. 2013 27 Differential Output Slew RateWith the reference load for timing measurements, output slew rate for falling and rising edges is

Rev. 1.1 / Jul. 2013 28 Reference Load for AC Timing and Output Slew RateFigure Below represents the effective reference load of 25 ohms used in defin

Rev. 1.1 / Jul. 2013 29 Overshoot and Undershoot SpecificationsAddress and Control Overshoot and Undershoot Specifications Address and Control Oversho

Rev. 1.1 / Jul. 2013 3 DescriptionSK hynix Unbuffered DDR3L SDRAM DIMMs (Unbuffered Double Data Rate Synchronous DRAM Dual In-Line Memory Modules) are

Rev. 1.1 / Jul. 2013 30 Clock, Data, Strobe and Mask Overshoot and Undershoot Specifications Clock, Data, Strobe and Mask Overshoot and Undershoot Def

Rev. 1.1 / Jul. 2013 31 Refresh parameters by device densityNotes:1. Users should refer to the DRAM supplier data sheet and/or the DIMM SPD to determi

Rev. 1.1 / Jul. 2013 32 Standard Speed BinsDDR3L SDRAM Standard Speed Bins include tCK, tRCD, tRP, tRAS and tRC for each corresponding bin.DDR3L-800 S

Rev. 1.1 / Jul. 2013 33 DDR3L-1066 Speed BinsFor specific Notes See "Speed Bin Table Notes" on page 36.Speed Bin DDR3L-1066FUnit NoteCL - nR

Rev. 1.1 / Jul. 2013 34 DDR3L-1333 Speed BinsFor specific Notes See "Speed Bin Table Notes" on page 36.Speed Bin DDR3L-1333HUnit NoteCL - nR

Rev. 1.1 / Jul. 2013 35 DDR3L-1600 Speed BinsFor specific Notes See "Speed Bin Table Notes" on page 36.Speed Bin DDR3L-1600KUnit NoteCL - nR

Rev. 1.1 / Jul. 2013 36 Speed Bin Table NotesAbsolute Specification (TOPER; VDDQ = VDD = 1.35V +0.100/- 0.067 V); 1. The CL setting and CWL setting re

Rev. 1.1 / Jul. 2013 37 Environmental ParametersNote: 1. Stress greater than those listed may cause permanent damage to the device. This is a stress r

Rev. 1.1 / Jul. 2013 38 IDD and IDDQ Specification Parameters and Test ConditionsIDD and IDDQ Measurement ConditionsIn this chapter, IDD and IDDQ meas

Rev. 1.1 / Jul. 2013 39 Measurement Setup and Test Load for IDD and IDDQ (optional) Measurements[Note: DIMM level Output test load condition may be d

Rev. 1.1 / Jul. 2013 4 Key Parameters*SK hynix DRAM devices support optional downbinning to CL9 and CL7. SPD setting is programmed to matchSpeed Grad

Rev. 1.1 / Jul. 2013 40 Table 1 -Timings used for IDD and IDDQ Measurement-Loop PatternsTable 2 -Basic IDD and IDDQ Measurement ConditionsSymbolDDR3L-

Rev. 1.1 / Jul. 2013 41 IDD2NPrecharge Standby CurrentCKE: High; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: stable at 1; Command, A

Rev. 1.1 / Jul. 2013 42 IDD4ROperating Burst Read CurrentCKE: High; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: High between RD; Com

Rev. 1.1 / Jul. 2013 43 a) Burst Length: BL8 fixed by MRS: set MR0 A[1,0]=00Bb) Output Buffer Enable: set MR1 A[12] = 0B; set MR1 A[5,1] = 01B; RTT_No

Rev. 1.1 / Jul. 2013 44 Table 3 - IDD0 Measurement-Loop Patterna)a) DM must be driven LOW all the time. DQS, DQS are MID-LEVEL.b) DQ signals are MID-L

Rev. 1.1 / Jul. 2013 45 Table 4 - IDD1 Measurement-Loop Patterna)a) DM must be driven LOW all the time. DQS, DQS are used according to RD Commands, ot

Rev. 1.1 / Jul. 2013 46 Table 5 - IDD2N and IDD3N Measurement-Loop Patterna)a) DM must be driven LOW all the time. DQS, DQS are MID-LEVEL.b) DQ signal

Rev. 1.1 / Jul. 2013 47 Table 7 - IDD4R and IDDQ4R Measurement-Loop Patterna)a) DM must be driven LOW all the time. DQS, DQS are used according to RD

Rev. 1.1 / Jul. 2013 48 Table 9 - IDD5B Measurement-Loop Patterna)a) DM must be driven LOW all the time. DQS, DQS are MID-LEVEL.b) DQ signals are MID-

Rev. 1.1 / Jul. 2013 49 Table 10 - IDD7 Measurement-Loop Patterna)ATTENTION! Sub-Loops 10-19 have inverse A[6:3] Pattern and Data Pattern than Sub-Loo

Rev. 1.1 / Jul. 2013 5 Pin DescriptionsPin Name Description Pin Name DescriptionA0–A15 SDRAM address bus SCL I2C serial bus clock for EEPROMBA0–BA2 SD

Rev. 1.1 / Jul. 2013 50 IDD Specifications (Tcase: 0 to 95oC)* Module IDD values in the datasheet are only a calculation based on the component IDD sp

Rev. 1.1 / Jul. 2013 51 Module Dimensions256Mx72 - HMT325U7CFR8A9.5017.30Max R0.702x2.50 0.10Min 1.45DETAIL-ADETAIL-B2.10 0.154x3.00 0.102x2.30 0.

Rev. 1.1 / Jul. 2013 52 512Mx72 - HMT351U7CFR8A9.5017.30Max R0.702x2.50 0.10Min 1.45DETAIL-ADETAIL-B2.10 0.154x3.00 0.102x2.30 0.105.17547.0071.0

Rev. 1.1 / Jul. 2013 6 Input/Output Functional DescriptionsSymbol Type Polarity FunctionCK0–CK1CK0–CK1SSTLDifferential crossingCK and CK are different

Rev. 1.1 / Jul. 2013 7 DQS0–DQS8DQS0–DQS8SSTLDifferential crossingData strobe for input and output data.SA0–SA2 —These signals are tied at the system

Rev. 1.1 / Jul. 2013 8 Pin AssignmentsFront Side(left 1–60) Back Side(right 121–180) Front Side(left 61–120) Back Side(right 181–240)Pin #x72 ECCPin #

Rev. 1.1 / Jul. 2013 9 31 DQ25 151VSS91 DQ41 211VSS32VSS152 DM3 92VSS212 DM533 DQS3153 NC 93 DQS5213 NC34 DQS3 154VSS94 DQS5 214VSS35VSS155 DQ30 95VSS