Hynix HMT31GR7CFR4A-PBT8 Datasheet Page 30

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Rev. 1.1 / May. 2013 30
Figure 0 - VDD/VDDQ Voltage Switch Between DDR3L and DDR3
NOTE 1: From time point Td until Tk NOP or DES commands must be applied
between MRS and ZQCL commands.
Ta
CK,CK#
RESET#
Tb Tc Td Te Tf Tg Th Ti Tj Tk
MRS1) 1)MRS MRS
CKE
DONT CARE
READ MRS
T = 500us
COMMAND
ODT
BA
RTT
MR3 MR1 MR0READ MR2
READ Static LOW in case RTT_Nom is enabled at time Tg, otherwise static HIGH or LOW
VDD, VDDQ (DDR3)
VDD, VDDQ (DDR3L)
ZQCL VALID
VALID
VALID
VALID
Tmin = 200us
Tmin = 10ns
Tmin = 10ns
tCKSRX
Tmin = 10ns
tIS
tIS tIS
tXPR tMRD tMRD tMRD tMOD tZQinit
tDLLK
TIME BREAK
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