Hynix HMT31GR7CFR4A-PBT8 Datasheet download pdf (Page 38)

Rev. 1.1 / May. 2013 38

Differential Input Cross Point Voltage

To guarantee tight setup and hold times as well as output skew parameters with respect to clock and

strobe, each cross point voltage of differential input signals (CK, CK

and DQS, DQS) must meet the

requirements in table below. The differential input cross point voltage VIX is measured from the actual

cross point of true and complement signals to the midlevel between of VDD and VSS

Vix Definition

Notes:

1. Extended range for V

is only allowed for clock and if single-ended clock input signals CK and CK are monotonic

with a single-ended swing VSEL / VSEH of at least VDD/2 +/-250 mV, and when the differential slew rate of CK -

CK is larger than 3 V/ns.

2. The relation between Vix Min/Max and VSEL/VSEH should satisfy following.

(VDD/2) + Vix (Min) - VSEL  25mV 

VSEH - ((VDD/2) + Vix (Max))  25mV

Cross point voltage for differential input signals (CK, DQS)

Symbol Parameter

DDR3L-800, 1066, 1333, 1600

Unit Notes

Min Max

(CK)

Differential Input Cross Point Voltage

relative to VDD/2 for CK,

-150 150 mV 2

-175 175 mV 1

(DQS)

Differential Input Cross Point Voltage

relative to VDD/2 for DQS,

DQS

-150 150 mV 2

1 2 ... 33 34 35 36 37 38 39 40 41 42 43 ... 75 76

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Hynix HMT31GR7CFR4A-PBT8 Datasheet Page 38