Rev. 1.1 / May. 2013 19
S0
S1
BA[N:0]
A[N:0]
RAS
CAS
WE
CKE0
ODT0
CK0
CK0
PAR_IN
CS0
→
CS0: SDRAMs U[10:2]
CS
1
→
CS1: SDRAMs U[19:11]
CS
2
→
CS2: SDRAMs U[28:20]
ERAS
→
RAS: SDRAMs U[10:7], U[19:16], U[28:25], U[37:34]
CS3
→
CS3: SDRAMs U[37:29]
EBA[N:0]
→
BA[N:0]: SDRAMs U[10:7], U[19:16], U[28:25], U[37:34]
WBA[N:0]
→
BA[N:0]: SDRAMs U[6:2], U[15:11], U[24:20], U[33:29]
WRAS
→
RAS: SDRAMs U[6:2], U[15:11], U[24:20], U[33:29]
ECAS
→
CAS: SDRAMs U[10:7], U[19:16], U[28:25], U[37:34]
WCAS
→
CAS: SDRAMs U[6:2], U[15:11], U[24:20], U[33:29]
EWE
→
WE: SDRAMs U[10:7], U[19:16], U[28:25], U[37:34]
WWE
→
WE: SDRAMs U[6:2], U[15:11], U[24:20], U[33:29]
ECKE0
→
CKE0: SDRAMs U[10:7], U[28:25]
WCKE0
→
CKE0: SDRAMs U[6:2], U[24:20]
EODT0
→
ODT0: SDRAMs U[10:7]
WODT0
→
ODT0: SDRAMs U[6:2]
PCK1
→
CK: SDRAMs U[10:7], U[28:25]
PCK0
→
CK: SDRAMs U[6:2], U[15:11]
PCK1
→
CK: SDRAMs U[10:7], U[28:25]
PCK0
→
CK: SDRAMs U[6:2], U[15:11]
Err_Out
RESET RST
RST: SDRAMs U[37:2]
1:2
R
E
G
I
S
T
E
R
/
P
ECKE1
→
CKE1: SDRAMs U[19:16], U[37:34]
WCKE1
→
CKE1: SDRAMs U[15:11], U[33:29]
ODT1
EODT0
→
ODT1: SDRAMs U[28:25]
WODT0
→
ODT1: SDRAMs U[24:20]
CKE1
EA[N:0]
→
A[N:0]: SDRAMs U[10:7], U[19:16], U[28:25], U[37:34]
WA[N:0]
→
A[N:0]: SDRAMs U[6:2], U[15:11], U[24:20], U[33:29]
PCK3
→
CK: SDRAMs U[19:16], U[37:34]
PCK2
→
CK: SDRAMs U[24:20], U[33:29]
PCK3
→
CK: SDRAMs U[19:16], U[37:34]
PCK2
→
CK: SDRAMs U[24:20], U[33:29]
L
L
CK1
CK1
120
Ω
±5%
S2
S3
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