Hynix HMT42GR7BFR4A-PBT4 Datasheet

Rev. 1.0 /May. 2014 1 240pin DDR3L SDRAM Registered DIMM*SK hynix reserves the right to change products or specifications without notice.DDR3L SDRAM

Rev. 1.0 / May. 2014 10 Registering Clock Driver SpecificationsCapacitance ValuesInput & Output Timing RequirementsSymbol Parameter Conditions Min

Rev. 1.0 / May. 2014 11 On DIMM Thermal SensorThe DDR3 SDRAM DIMM temperature is monitored by integrated thermal sensor. The integrated thermal sensor

Rev. 1.0 / May. 2014 12 Functional Block Diagram4GB, 512Mx72 Module(1Rank of x8)CB[7:0]DQS8DQS8DM8/DQS17DQS17RRASARCASARS0ARWEAPCK0APCK0ARCKE0ARODT0AA

Rev. 1.0 / May. 2014 13 8GB, 1Gx72 Module(1Rank of x4) - page1RRASARCASARS0ARWEAPCK0APCK0ARCKE0ARODT0AA[O:N]AVtt/BA[O:N]ACB[3:0]DQS8DQS8DQSDQSDMD8DQ [

Rev. 1.0 / May. 2014 14 8GB, 1Gx72 Module(1Rank of x4) - page2S0S1BA[N:0]A[N:0]RASCASWECKE0ODT0CK0CK0PAR_INRS0A →CS0: SDRAMs D[3:0], D[12:8], D17RS0B

Rev. 1.0 / May. 2014 15 8GB, 1Gx72 Module(2Rank of x8) - page1DQSDQSTDQSTDQSD17DQ [7:0]ZQRASCASCSWECKCKCKEODTA[N:O]/BA[N:O]RRASARCASARS0ARWEAPCK0APCK0

Rev. 1.0 / May. 2014 16 8GB, 1Gx72(2Rank of x8) - page2S0S1BA[N:0]A[N:0]RASCASWECKE0ODT0CK0CK0PAR_INRS0A →CS0: SDRAMs D[3:0], D8RS0B → CS0: SDRAMs D[7

Rev. 1.0 / May. 2014 17 16GB, 2Gx72 Module(2Rank of x4) - page1RRASARCASARS0ARWEAPCK0APCK0ARCKE0ARODT0AA[O:N]A/BA[O:N]ACB[7:4]DQS17DQS17DQSDQSDMD17DQ

Rev. 1.0 / May. 2014 18 16GB, 2Gx72 Module(2Rank of x4) - page2D0–D35VDDD0–D35VTTVDDSPDD0–D35VREFDQSPDVREFCAVSSD0–D35D0–D35Note:1. DQ-to-I/O wiring ma

Rev. 1.0 / May. 2014 19 16GB, 2Gx72 Module(2Rank of x4) - page3S0S1BA[N:0]A[N:0]RASCASWECKE0ODT0CK0CK0PAR_INRS0A →CS0: SDRAMs D[3:0], D[12:8], D17RS0B

Rev. 1.0 / May. 2014 2 Revision HistoryRevision No. History Draft Date Remark0.1 Initial Release Mar.20141.0 Revision 1.0 Release May.2014

Rev. 1.0 / May. 2014 20 32GB, 4Gx72 Module(4Rank of x4) - page1ZQARRASAARCASAARS0AARWEAAPCK0AAPCK0AARCKE0AARODT0AARA[N:O]AVtt/ARBA[N:O]ACB[3:0]DQS8DQS

Rev. 1.0 / May. 2014 21 32GB, 4Gx72 Module(4Rank of x4) - page2ZQARRASAARCASAARS0AARWEAAPCK0AAPCK0AARCKE0AARODT0AARA[N:O]AVtt/ARBA[N:O]ACB[7:4]DQS17DQ

Rev. 1.0 / May. 2014 22 32GB, 4Gx72 Module(4Rank of x4) - page3ZQARRASBARCASBARS0BARWEBAPCK0BAPCK0BARCKE0BARODT0BARA[N:O]BVtt/ARBA[N:O]BDQ[35:32]DQS4D

Rev. 1.0 / May. 2014 23 32GB, 4Gx72 Module(4Rank of x4) - page4ZQARRASBARCASBARS0BARWEBAPCK0BAPCK0BARCKE0BARODT0BARA[N:O]BVtt/ARBA[N:O]BDQ[39:36]DQS13

Rev. 1.0 / May. 2014 24 32GB, 4Gx72 Module(4Rank of x4) - page5CK1CK1120Ω±5%S2S3BA[N:0]A[N:0]RASCASWECKE0CK0CK0PAR_INBRS2A →CS1: SDRAMs D45,D47,D49,D5

Rev. 1.0 / May. 2014 25 Absolute Maximum RatingsAbsolute Maximum DC RatingsNotes:1. Stresses greater than those listed under “Absolute Maximum Ratings

Rev. 1.0 / May. 2014 26 AC & DC Operating ConditionsRecommended DC Operating ConditionsRecommended DC Operating Conditions - DDR3L (1.35V) operati

Rev. 1.0 / May. 2014 27 Figure 0 - VDD/VDDQ Voltage Switch Between DDR3L and DDR3NOTE 1: From time point “Td” until “Tk” NOP or DES commands must be a

Rev. 1.0 / May. 2014 28 AC & DC Input Measurement LevelsAC and DC Logic Input Levels for Single-Ended SignalsAC and DC Input Levels for Single-End

Rev. 1.0 / May. 2014 29 AC and DC Input Levels for Single-Ended SignalsDDR3 SDRAM will support two Vih/Vil AC levels for DDR3-800 and DDR3-1066s speci

Rev. 1.0 / May. 2014 3 DescriptionSK hynix Registered DDR3L SDRAM DIMMs (Registered Double Data Rate Synchronous DRAM Dual In-Line Memory Modules) are

Rev. 1.0 / May. 2014 30 Vref TolerancesThe dc-tolerance limits and ac-noise limits for the reference voltages VRefCA and VRefDQ are illustrated in fig

Rev. 1.0 / May. 2014 31 AC and DC Logic Input Levels for Differential SignalsDifferential signal definitionDefinition of differential ac-swing and “ti

Rev. 1.0 / May. 2014 32 Differential swing requirements for clock (CK - CK) and strobe (DQS-DQS)Notes:1. Used to define a differential signal slew-rat

Rev. 1.0 / May. 2014 33 Single-ended requirements for differential signalsEach individual component of a differential signal (CK, DQS, DQSL, DQSU, CK,

Rev. 1.0 / May. 2014 34 Notes:1. For CK, CK use VIH/VIL (ac) of ADD/CMD; for strobes (DQS, DQS, DQSL, DQSL, DQSU, DQSU) use VIH/VIL (ac) of DQs.2. VIH

Rev. 1.0 / May. 2014 35 Differential Input Cross Point VoltageTo guarantee tight setup and hold times as well as output skew parameters with respect t

Rev. 1.0 / May. 2014 36 Slew Rate Definitions for Single-Ended Input SignalsSee 7.5 “Address / Command Setup, Hold and Derating” in “DDR3 Device Opera

Rev. 1.0 / May. 2014 37 AC & DC Output Measurement LevelsSingle Ended AC and DC Output LevelsTable below shows the output levels used for measurem

Rev. 1.0 / May. 2014 38 Single Ended Output Slew RateWhen the Reference load for timing measurements, output slew rate for falling and rising edges is

Rev. 1.0 / May. 2014 39 Differential Output Slew RateWith the reference load for timing measurements, output slew rate for falling and rising edges is

Rev. 1.0 / May. 2014 4 Key Parameters*SK hynix DRAM devices support optional downbinning to CL11, CL9 and CL7. SPD setting is programmed to match.Spee

Rev. 1.0 / May. 2014 40 Reference Load for AC Timing and Output Slew RateFigure below represents the effective reference load of 25 ohms used in defin

Rev. 1.0 / May. 2014 41 Overshoot and Undershoot SpecificationsAddress and Control Overshoot and Undershoot SpecificationsAddress and Control Overshoo

Rev. 1.0 / May. 2014 42 Clock, Data, Strobe and Mask Overshoot and Undershoot SpecificationsClock, Data, Strobe and Mask Overshoot and Undershoot Defi

Rev. 1.0 / May. 2014 43 Refresh parameters by device densityNotes:1. Users should refer to the DRAM supplier data sheet and/or the DIMM SPD to determi

Rev. 1.0 / May. 2014 44 Standard Speed BinsDDR3 SDRAM Standard Speed Bins include tCK, tRCD, tRP, tRAS and tRC for each corresponding bin.DDR3L-800 Sp

Rev. 1.0 / May. 2014 45 DDR3L-1066 Speed BinsFor specific Notes See "Speed Bin Table Notes" on page 49.Speed Bin DDR3L-1066FUnit NoteCL - nR

Rev. 1.0 / May. 2014 46 DDR3L-1333 Speed BinsFor specific Notes See "Speed Bin Table Notes" on page 49.Speed Bin DDR3L-1333HUnit NoteCL - nR

Rev. 1.0 / May. 2014 47 DDR3L-1600 Speed BinsFor specific Notes See "Speed Bin Table Notes" on page 49.Speed Bin DDR3L-1600KUnit NoteCL - nR

Rev. 1.0 / May. 2014 48 DDR3L-1866 Speed BinsFor specific Notes See "Speed Bin Table Notes" on page 49.Speed Bin DDR3L-1866MUnit NoteCL - nR

Rev. 1.0 / May. 2014 49 Speed Bin Table NotesAbsolute Specification (TOPER; VDDQ = VDD = 1.35V +0.100/- 0.067 V); 1. The CL setting and CWL setting re

Rev. 1.0 / May. 2014 5 Pin DescriptionsPin Name DescriptionNumberPin Name DescriptionNumberCK0 Clock Input, positive line 1 ODT[1:0] On Die Terminat

Rev. 1.0 / May. 2014 50 Environmental ParametersNote: 1. Stress greater than those listed may cause permanent damage to the device. This is a stress r

Rev. 1.0 / May. 2014 51 IDD and IDDQ Specification Parameters and Test ConditionsIDD and IDDQ Measurement ConditionsIn this chapter, IDD and IDDQ meas

Rev. 1.0 / May. 2014 52 Figure 1 - Measurement Setup and Test Load for IDD and IDDQ (optional) Measurements[Note: DIMM level Output test load conditio

Rev. 1.0 / May. 2014 53 Table 1 -Timings used for IDD and IDDQ Measurement-Loop PatternsTable 2 -Basic IDD and IDDQ Measurement ConditionsSymbolDDR3L-

Rev. 1.0 / May. 2014 54 IDD2NPrecharge Standby CurrentCKE: High; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: stable at 1; Command, A

Rev. 1.0 / May. 2014 55 IDD4ROperating Burst Read CurrentCKE: High; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: High between RD; Com

Rev. 1.0 / May. 2014 56 a) Burst Length: BL8 fixed by MRS: set MR0 A[1,0]=00Bb) Output Buffer Enable: set MR1 A[12] = 0B; set MR1 A[5,1] = 01B; RTT_No

Rev. 1.0 / May. 2014 57 Table 3 - IDD0 Measurement-Loop Patterna)a) DM must be driven LOW all the time. DQS, DQS are MID-LEVEL.b) DQ signals are MID-L

Rev. 1.0 / May. 2014 58 Table 4 - IDD1 Measurement-Loop Patterna)a) DM must be driven LOW all the time. DQS, DQS are used according to RD Commands, ot

Rev. 1.0 / May. 2014 59 Table 5 - IDD2N and IDD3N Measurement-Loop Patterna)a) DM must be driven LOW all the time. DQS, DQS are MID-LEVEL.b) DQ signal

Rev. 1.0 / May. 2014 6 Input/Output Functional DescriptionsSymbol Type Polarity FunctionCK0 INPositiveLinePositive line of the differential pair of sy

Rev. 1.0 / May. 2014 60 Table 7 - IDD4R and IDDQ4R Measurement-Loop Patterna)a) DM must be driven LOW all the time. DQS, DQS are used according to RD

Rev. 1.0 / May. 2014 61 Table 9 - IDD5B Measurement-Loop Patterna)a) DM must be driven LOW all the time. DQS, DQS are MID-LEVEL.b) DQ signals are MID-

Rev. 1.0 / May. 2014 62 Table 10 - IDD7 Measurement-Loop Patterna)ATTENTION! Sub-Loops 10-19 have inverse A[6:3] Pattern and Data Pattern than Sub-Loo

Rev. 1.0 / May. 2014 63 IDD Specifications (Tcase: 0 to 95oC)* Module IDD values in the datasheet are only a calculation based on the component IDD sp

Rev. 1.0 / May. 2014 64 8GB, 1G x 72 R-DIMM: HMT41GR7BFR8A16GB, 2G x 72 R-DIMM: HMT42GR7BFR4ASymbol DDR3L 1333 DDR3L 1600 DDR3L 1866 Unit noteIDD0 111

Rev. 1.0 / May. 2014 65 32GB, 4G x 72 R-DIMM: HMT84GR7BMR4ASymbol DDR3L 1066 DDR3L 1333 DDR3L 1600 Unit noteIDD0 1916 1934 2150 mAIDD1 2060 2078 2294

Rev. 1.0 / May. 2014 66 Module Dimensions512Mx72 - HMT451R7BFR8A5.175Detail C2.10±0.1547.0071.002X3.00±0.10Front130.009.5017.301205.011240121Back133.3

Rev. 1.0 / May. 2014 67 1Gx72 - HMT41GR7BFR4A5.175Detail BDetail C2.10±0.1547.0071.002X3.00±0.10Front14X3.00±0.101205.011240121Back133.35128.95Registe

Rev. 1.0 / May. 2014 68 1Gx72 - HMT41GR7BFR8A5.175Detail BDetail C2.10±0.1547.0071.002X3.00±0.10Front14X3.00±0.101205.011240121Back133.35128.95Registe

Rev. 1.0 / May. 2014 69 2Gx72 - HMT42GR7BFR4A30.009.5017.3023.305.175Detail CDetail D2.10±0.1547.0071.002X3.00±0.10Front11205.011240121Back133.35128.9

Rev. 1.0 / May. 2014 7 DQS[17:0] I/OPositiveEdgePositive line of the differential data strobe for input and output data.DQS[17:0]I/ONegativeEdgeNegati

Rev. 1.0 / May. 2014 70 2Gx72 - HMT42GR7BFR4A - Heat SpreaderFront30.20120Back133.3522.00RegisteringClock Driver127121RegisteringClock Driver1.27±010m

Rev. 1.0 / May. 2014 71 4Gx72 - HMT84GR7BMR4A30.009.5017.3023.305.175Detail CDetail D2.10±0.1547.0071.002X3.00±0.10Front11205.011240121Back133.35128.9

Rev. 1.0 / May. 2014 72 4Gx72 - HMT84GR7BMR4A - Heat SpreaderFront30.20120Back133.3522.00RegisteringClock Driver127121RegisteringClock Driver1.27±010m

Rev. 1.0 / May. 2014 8 Pin AssignmentsPin #Front Side(left 1–60)Pin #Back Side(right 121–180)Pin #Front Side(left 61–120)Pin #Back Side(right 181–240)

Rev. 1.0 / May. 2014 9 32VSS152DM3,DQS12,TDQS1292VSS212DM5,DQS14,TDQS1433 DQS3153NC,DQS12,TDQS1293 DQS5 213NC,DQS14,TDQS1434 DQS3 154VSS94 DQS5 214VSS