Hynix HMT351U6BFR8C-H9N0 Datasheet Page 43
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Rev. 1.0 / Oct. 2010 43
I
DD2N
Precharge Standby Current
CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8
a)
; AL: 0; CS: stable at 1; Command, Address, Bank
Address Inputs: partially toggling according to Table 5; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all
banks closed; Output Buffer and RTT: Enabled in Mode Registers
b)
; ODT Signal: stable at 0; Pattern Details:
see Table 5.
I
DD2NT
Precharge Standby ODT Current
CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8
a)
; AL: 0; CS: stable at 1; Command, Address, Bank
Address Inputs: partially toggling according to Table 6; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all
banks closed; Output Buffer and RTT: Enabled in Mode Registers
b)
; ODT Signal: toggling according to Table 6;
Pattern Details: see Table 6.
I
DD2P0
Precharge Power-Down Current Slow Exit
CKE: Low; External clock: On; tCK, CL: see Table 1; BL: 8
a)
; AL: 0; CS: stable at 1; Command, Address, Bank
Address Inputs: stable at 0; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all banks closed; Output
Buffer and RTT: Enabled in Mode Registers
b)
; ODT Signal: stable at 0; Precharge Power Down Mode: Slow
Exit
c)
I
DD2P1
Precharge Power-Down Current Fast Exit
CKE: Low; External clock: On; tCK, CL: see Table 1; BL: 8
a)
; AL: 0; CS: stable at 1; Command, Address, Bank
Address Inputs: stable at 0; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all banks closed; Output
Buffer and RTT: Enabled in Mode Registers
b)
; ODT Signal: stable at 0; Precharge Power Down Mode: Fast Exit
c)
I
DD2Q
Precharge Quiet Standby Current
CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8
a)
; AL: 0; CS: stable at 1; Command, Address, Bank
Address Inputs: stable at 0; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all banks closed; Output
Buffer and RTT: Enabled in Mode Registers
b)
; ODT Signal: stable at 0
I
DD3N
Active Standby Current
CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8
a)
; AL: 0; CS: stable at 1; Command, Address, Bank
Address Inputs: partially toggling according to Table 5; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all
banks open; Output Buffer and RTT: Enabled in Mode Registers
b)
; ODT Signal: stable at 0; Pattern Details: see
Table 5.
I
DD3P
Active Power-Down Current
CKE: Low; External clock: On; tCK, CL: see Table 1; BL: 8
a)
; AL: 0; CS: stable at 1; Command, Address, Bank
Address Inputs: stable at 0; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all banks open; Output Buffer
and RTT: Enabled in Mode Registers
b)
; ODT Signal: stable at 0
Symbol Description
B48614/178.104.2.80/2010-10-18 17:08
- DDR3 SDRAM 1
- Unbuffered DIMMs 1
- Based on 2Gb B-Die 1
- Revision History 2
- Ordering Information 3
- Key Parameters 4
- Speed Grade 4
- Address Table 4
- Pin Descriptions 5
- Rev. 1.0 / Oct. 2010 6 6
- Pin Assignments 7
- Rev. 1.0 / Oct. 2010 8 8
- Rev. 1.0 / Oct. 2010 9 9
- On DIMM Thermal Sensor 10
- Functional Block Diagram 11
- Absolute Maximum Ratings 16
- RefCA(DC 17
- Rev. 1.0 / Oct. 2010 18 18
- RefDQ(DC) 18
- Vref Tolerances 19
- Rev. 1.0 / Oct. 2010 21 21
- Rev. 1.0 / Oct. 2010 22 22
- Rev. 1.0 / Oct. 2010 23 23
- Rev. 1.0 / Oct. 2010 24 24
- Description 25
- Measured 25
- Rev. 1.0 / Oct. 2010 27 27
- Differential Output Slew Rate 28
- Rev. 1.0 / Oct. 2010 29 29
- Rev. 1.0 / Oct. 2010 30 30
- (CK, CK, DQ, DQS, DQS, DM) 31
- °C < T 32
- Standard Speed Bins 33
- Rev. 1.0 / Oct. 2010 34 34
- Rev. 1.0 / Oct. 2010 35 35
- Rev. 1.0 / Oct. 2010 36 36
- Speed Bin Table Notes 37
- Environmental Parameters 38
- 1GB: HMT312U6BFR6C 39
- 2GB: HMT325U6BFR8C 39
- 2GB: HMT325U7BFR8C 39
- 4GB: HMT351U6BFR8C 39
- 4GB: HMT351U7BFR8C 39
- Rev. 1.0 / Oct. 2010 40 40
- ILAC(max) 40
- IHAC(max) 40
- Rev. 1.0 / Oct. 2010 41 41
- Rev. 1.0 / Oct. 2010 42 42
- Rev. 1.0 / Oct. 2010 43 43
- Rev. 1.0 / Oct. 2010 44 44
- Rev. 1.0 / Oct. 2010 45 45
- Rev. 1.0 / Oct. 2010 46 46
- Rev. 1.0 / Oct. 2010 47 47
- Rev. 1.0 / Oct. 2010 48 48
- Rev. 1.0 / Oct. 2010 49 49
- Rev. 1.0 / Oct. 2010 50 50
- Rev. 1.0 / Oct. 2010 52 52
- Rev. 1.0 / Oct. 2010 53 53
- Rev. 1.0 / Oct. 2010 54 54
- Module Dimensions 55
- 256Mx64 - HMT325U6BFR8C 56
- 256Mx72 - HMT325U7BFR8C 57
- 512Mx64 - HMT351U6BFR8C 58
- 512Mx72 - HMT351U7BFR8C 59
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