Hynix HMT351U6BFR8C-H9N0 Datasheet download pdf (Page 21)

APCPCWM_4828539:WP_0000005WP_0000005

Rev. 1.0 / Oct. 2010 21

Differential swing requirements for clock (CK - CK) and strobe (DQS-DQS)

Notes:

1. Used to define a differential signal slew-rate.

2. For CK - CK use VIH/VIL (ac) of AADD/CMD and VREFCA; for DQS - DQS, DQSL, DQSL, DQSU, DQSU use VIH/VIL

(ac) of DQs and VREFDQ; if a reduced ac-high or ac-low levels is used for a signal group, then the reduced level

applies also here.

3. These values are not defined; however, the single-ended signals Ck, CK, DQS, DQS, DQSL, DQSL, DQSU, DQSU

need to be within the respective limits (VIH (dc) max, VIL (dc) min) for single-ended signals as well as the limita

tions for overshoot and undershoot. Refer to “Overshoot and Undershoot Specifications” on page 30.

Differential AC and DC Input Levels

Symbol Parameter

DDR3-800, 1066, 1333, & 1600

Unit Notes

Min Max

VIHdiff Differential input high + 0.200 Note 3 V 1

VILdiff Differential input logic low Note 3 - 0.200 V 1

VIHdiff (ac) Differential input high ac 2 x (VIH (ac) - Vref) Note 3 V 2

VILdiff (ac) Differential input low ac Note 3 2 x (VIL (ac) - Vref) V 2

Allowed time before ringback (tDVAC) for CK - CK and DQS - DQS

Slew Rate [V/ns]

tDVAC [ps]

@ |VIH/Ldiff (ac)| = 350mV

tDVAC [ps]

@ |VIH/Ldiff (ac)| = 300mV

min max min max

> 4.0 75 - 175 -

4.0 57 - 170 -

3.0 50 - 167 -

2.0 38 - 163

1.8 34 - 162 -

1.6 29 - 161 -

1.4 22 - 159 -

1.2 13 - 155 -

1.0 0 - 150 -

< 1.0 0 - 150 -

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Hynix HMT351U6BFR8C-H9N0 Datasheet Page 21