Hynix HMT351S6CFR8C-PB Datasheet Page 37
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Rev. 1.0/Sep. 2012 37
I
DD2N
Precharge Standby Current
CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8
a)
; AL: 0; CS: stable at 1; Command, Address, Bank
Address Inputs: partially toggling according to Table 5; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all
banks closed; Output Buffer and RTT: Enabled in Mode Registers
b)
; ODT Signal: stable at 0; Pattern Details:
see Table 5.
I
DD2NT
Precharge Standby ODT Current
CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8
a)
; AL: 0; CS: stable at 1; Command, Address, Bank
Address Inputs: partially toggling according to Table 6; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all
banks closed; Output Buffer and RTT: Enabled in Mode Registers
b)
; ODT Signal: toggling according to Table 6;
Pattern Details: see Table 6.
I
DD2P0
Precharge Power-Down Current Slow Exit
CKE: Low; External clock: On; tCK, CL: see Table 1; BL: 8
a)
; AL: 0; CS: stable at 1; Command, Address, Bank
Address Inputs: stable at 0; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all banks closed; Output Buf-
fer and RTT: Enabled in Mode Registers
b)
; ODT Signal: stable at 0; Precharge Power Down Mode: Slow Exit
c)
I
DD2P1
Precharge Power-Down Current Fast Exit
CKE: Low; External clock: On; tCK, CL: see Table 1; BL: 8
a)
; AL: 0; CS: stable at 1; Command, Address, Bank
Address Inputs: stable at 0; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all banks closed; Output Buf-
fer and RTT: Enabled in Mode Registers
b)
; ODT Signal: stable at 0; Precharge Power Down Mode: Fast Exit
c)
I
DD2Q
Precharge Quiet Standby Current
CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8
a)
; AL: 0; CS: stable at 1; Command, Address, Bank
Address Inputs: stable at 0; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all banks closed; Output Buf-
fer and RTT: Enabled in Mode Registers
b)
; ODT Signal: stable at 0
I
DD3N
Active Standby Current
CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8
a)
; AL: 0; CS: stable at 1; Command, Address, Bank
Address Inputs: partially toggling according to Table 5; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all
banks open; Output Buffer and RTT: Enabled in Mode Registers
b)
; ODT Signal: stable at 0; Pattern Details: see
Table 5.
I
DD3P
Active Power-Down Current
CKE: Low; External clock: On; tCK, CL: see Table 1; BL: 8
a)
; AL: 0; CS: stable at 1; Command, Address, Bank
Address Inputs: stable at 0; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all banks open; Output Buffer
and RTT: Enabled in Mode Registers
b)
; ODT Signal: stable at 0
Symbol Description
- DDR3 SDRAM 1
- Unbuffered SODIMMs 1
- Based on 2Gb C-die 1
- Revision History 2
- Ordering Information 3
- Key Parameters 4
- Speed Grade 4
- Address Table 4
- Pin Descriptions 5
- Symbol Type Polarity Function 6
- Pin Assignments 8
- Functional Block Diagram 9
- Rev. 1.0/Sep. 2012 10 10
- Absolute Maximum Ratings 11
- Rev. 1.0/Sep. 2012 12 12
- Rev. 1.0/Sep. 2012 13 13
- RefCA(DC) 13
- RefDQ(DC) 14
- Rev. 1.0/Sep. 2012 14 14
- Vref Tolerances 15
- Rev. 1.0/Sep. 2012 17 17
- Rev. 1.0/Sep. 2012 18 18
- Rev. 1.0/Sep. 2012 19 19
- Rev. 1.0/Sep. 2012 20 20
- Description 21
- Measured 21
- Single Ended Output Slew Rate 23
- Differential Output Slew Rate 24
- Rev. 1.0/Sep. 2012 25 25
- Rev. 1.0/Sep. 2012 26 26
- Rev. 1.0/Sep. 2012 27 27
- Rev. 1.0/Sep. 2012 28 28
- Standard Speed Bins 29
- DDR3-1066 Speed Bins 30
- DDR3-1333 Speed Bins 31
- DDR3-1600 Speed Bins 32
- Speed Bin Table Notes 33
- Rev. 1.0/Sep. 2012 34 34
- ILAC(max) 34
- IHAC(max) 34
- Rev. 1.0/Sep. 2012 35 35
- Rev. 1.0/Sep. 2012 36 36
- Rev. 1.0/Sep. 2012 37 37
- Rev. 1.0/Sep. 2012 38 38
- Rev. 1.0/Sep. 2012 39 39
- Rev. 1.0/Sep. 2012 40 40
- Rev. 1.0/Sep. 2012 41 41
- Rev. 1.0/Sep. 2012 42 42
- Rev. 1.0/Sep. 2012 43 43
- Rev. 1.0/Sep. 2012 44 44
- Rev. 1.0/Sep. 2012 46 46
- Module Dimensions 47
- 512Mx64 - HMT351S6CFR8C 48
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