Hynix HMT351R7BFR4C-PBT8 Datasheet download pdf (Page 57)

Rev. 1.5 / Mar. 2012 57

a) Burst Length: BL8 fixed by MRS: set MR0 A[1,0]=00B

b) Output Buffer Enable: set MR1 A[12] = 0B; set MR1 A[5,1] = 01B; RTT_Nom enable: set MR1 A[9,6,2]

= 011B; RTT_Wr enable: set MR2 A[10,9] = 10B

c) Precharge Power Down Mode: set MR0 A12=0B for Slow Exit or MR0 A12 = 1B for Fast Exit

d) Auto Self-Refresh (ASR): set MR2 A6 = 0B to disable or 1B to enable feature

e) Self-Refresh Temperature Range (SRT): set MR2 A7 = 0B for normal or 1B for extended temperature

range

f) Read Burst Type: Nibble Sequential, set MR0 A[3] = 0B

DD7

Operating Bank Interleave Read Current

CKE: High; External clock: On; tCK, nRC, nRAS, nRCD, NRRD, nFAW, CL: see Table 1; BL: 8

a),f)

; AL: CL-1; CS:

High between ACT and RDA; Command, Address, Bank Address Inputs: partially toggling according to Table

10; Data IO: read data burst with different data between one burst and the next one according to Table 10;

DM: stable at 0; Bank Activity: two times interleaved cycling through banks (0, 1,...7) with different address-

ing, wee Table 10; Output Buffer and RTT: Enabled in Mode Registers

; ODT Signal: stable at 0; Pattern

Details: see Table 10.

Symbol Description

1 2 ... 52 53 54 55 56 57 58 59 60 61 62 ... 74 75

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Hynix HMT351R7BFR4C-PBT8 Datasheet Page 57