Hynix HMT351R7BFR4C-PBT8 Datasheet Page 31
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Rev. 1.5 / Mar. 2012 31
AC and DC Input Levels for Single-Ended Signals
DDR3 SDRAM will support two Vih/Vil AC levels for DDR3-800 and DDR3-1066 as specified in the table
below. DDR3 SDRAM will also support corresponding tDS values (Table 41 and Table 47 in “ DDR3 Device
Operation”) as well as derating tables in Table 44 of “DDR3 Device Operation” depending on Vih/Vil AC lev-
els.
Notes:
1. Vref = VrefDQ (DC).
2. Refer to "Overshoot and Undershoot Specifications" on page 43.
3. The ac peak noise on V
Ref
may not allow V
Ref
to deviate from V
RefDQ(DC)
by more than +/-1% VDD (for
reference: approx. +/- 15 mV).
4. For reference: approx. VDD/2 +/- 15 mV.
5. VIH(dc) is used as a simplified symbol for VIH.DQ(DC100)
6. VIL(dc) is used as a simplified symbol for VIL.DQ(DC100)
7. VIH(ac) is used as simplified symbol for VIH.DQ(AC175), VIH.DQ(AC150), and VIH.DQ(AC135);
VIH.DQ(AC175) value is used when Vref + 0.175V is referenced, VIH.DQ(AC150) value is used when Vref
+ 0.150V is referenced, and VIH.DQ(AC135) value is used when Vref + 0.135V is referenced.
8. VIL(ac) is used as simplified symbol for VIL.DQ(AC175), VIL.DQ(AC150), and VIL.DQ(AC135);
VIL.DQ(AC175) value is used when Vref - 0.175V is referenced, VIL.DQ(AC150) value is used when Vref -
0.150V is referenced, and VIL.DQ(AC135) value is used when Vref - 0.135V is referenced.
9. Vref is measured relative to VDD at the same point, time and same device.
Single Ended AC and DC Input Levels for DQ and DM
Symbol Parameter
DDR3-800/1066 DDR3-1333/1600
Unit Notes
Min Max Min Max
VIH.DQ(DC100) DC input logic high Vref + 0.100 VDD Vref + 0.100 VDD V 1, 5
VIL.DQ(DC100) DC input logic low VSS Vref - 0.100 VSS Vref - 0.100 V 1, 6
VIH.DQ(AC175) AC input logic high Vref + 0.175 Note2 - - V 1, 2, 7
VIL.DQ(AC175) AC input logic low Note2 Vref - 0.175 - - V 1, 2, 8
VIH.DQ(AC150) AC Input logic high Vref + 0.150 Note2 Vref + 0.150 Note2 V 1, 2, 7
VIL.DQ(AC150) AC input logic low Note2 Vref - 0.150 Note2 Vref - 0.150 V 1, 2, 8
VIH.CA(AC135) AC input logic high - - - - mV 1, 2, 7
VIL.CA(AC135) AC input logic low - - - - mV 1, 2, 8
V
RefDQ(DC
)
Reference Voltage
for DQ, DM inputs
0.49 * VDD 0.51 * VDD 0.49 * VDD 0.51 * VDD V 3, 4, 9
- DDR3 SDRAM Registered DIMM 1
- Based on 2Gb B-die 1
- Revision History 2
- Description 3
- Features 3
- Ordering Information 3
- Key Parameters 4
- Speed Grade 4
- Address Table 4
- Pin Descriptions 5
- Symbol Type Polarity Function 6
- Pin Assignments 8
- Capacitance Values 10
- On DIMM Thermal Sensor 11
- Functional Block Diagram 12
- Rev. 1.5 / Mar. 2012 14 14
- Rev. 1.5 / Mar. 2012 15 15
- Rev. 1.5 / Mar. 2012 16 16
- Rev. 1.5 / Mar. 2012 17 17
- Rev. 1.5 / Mar. 2012 18 18
- Rev. 1.5 / Mar. 2012 19 19
- Rev. 1.5 / Mar. 2012 20 20
- Rev. 1.5 / Mar. 2012 22 22
- Rev. 1.5 / Mar. 2012 23 23
- Rev. 1.5 / Mar. 2012 24 24
- Rev. 1.5 / Mar. 2012 25 25
- Rev. 1.5 / Mar. 2012 27 27
- Absolute Maximum Ratings 28
- Rev. 1.5 / Mar. 2012 29 29
- Rev. 1.5 / Mar. 2012 30 30
- RefCA(DC) 30
- Rev. 1.5 / Mar. 2012 31 31
- RefDQ(DC) 31
- Vref Tolerances 32
- Rev. 1.5 / Mar. 2012 34 34
- Rev. 1.5 / Mar. 2012 35 35
- Rev. 1.5 / Mar. 2012 36 36
- Rev. 1.5 / Mar. 2012 37 37
- Measured 38
- Single Ended Output Slew Rate 40
- Differential Output Slew Rate 41
- Rev. 1.5 / Mar. 2012 42 42
- Rev. 1.5 / Mar. 2012 43 43
- Rev. 1.5 / Mar. 2012 44 44
- Rev. 1.5 / Mar. 2012 45 45
- Standard Speed Bins 46
- DDR3-1066 Speed Bins 47
- DDR3-1333 Speed Bins 48
- DDR3-1600 Speed Bins 49
- Speed Bin Table Notes 50
- Environmental Parameters 51
- Rev. 1.5 / Mar. 2012 52 52
- ILAC(max) 52
- IHAC(max) 52
- Rev. 1.5 / Mar. 2012 53 53
- Rev. 1.5 / Mar. 2012 54 54
- Rev. 1.5 / Mar. 2012 55 55
- Rev. 1.5 / Mar. 2012 56 56
- Rev. 1.5 / Mar. 2012 57 57
- Rev. 1.5 / Mar. 2012 58 58
- Rev. 1.5 / Mar. 2012 59 59
- Rev. 1.5 / Mar. 2012 60 60
- Rev. 1.5 / Mar. 2012 61 61
- Rev. 1.5 / Mar. 2012 62 62
- Rev. 1.5 / Mar. 2012 64 64
- Rev. 1.5 / Mar. 2012 65 65
- Rev. 1.5 / Mar. 2012 66 66
- Module Dimensions 67
- Units: millimeters 68
- 33.4 33.4 71
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